1. Field of the Invention
The invention relates to a circuit array for amplifying and holding data with different supply voltages.
Such circuits are for the most part constructed as bistable trigger circuits and have therefore been known for a long time. They are described, for instance, in the book by Tietze and Schenk entitled: Halbleiterschaltungstechnik [Semiconductor Circuitry], 1986, 8th edition, starting on p. 166.
Increasing semiconductor memory densities of integrated memories requires an ever-increasing packing density of memory cells and with it smaller transistors. For dependability reasons, the supply voltage of the minimal transistors must be reduced. However, the user wishes to operate with a supply voltage of 5 volts. Thus it has become necessary to reduce the supply voltage on the semiconductor memory. Consequently there are circuits on the memory that are operated with the external, high supply voltage, and circuits that operate with the internal, reduced supply voltage.
Semiconductor memories are organized in matrix arrays. Each individual memory cell can be addressed through a word line (WL) and a bitline pair (BL). Access to a memory cell of this type is effected by means of entering an address associated with the memory cell onto the semiconductor memory and entering a row address strobe (RAS) and a column address strobe (CAS). Usually the row or word address of the memory cell is selected with the RAS signal. Afterwards the column address is validated with the CAS signal, and the memory cell is thus fixed.
The memory cells addressed through a word line are read out and amplified. The bitline pairs selected through the column address are connected to a further line pair. They are generally referred to as external bitlines. In order to speed up the readout process, the signals to those lines are amplified and then switched further to the data output. In order to reduce the chip surface, the cell field includes a minimum of transistors and structures. The voltage is reduced in the cell field as described above. Therefore, it is necessary to accordingly adapt the voltage level of the data on the data path from the memory cell of data output.